Qorvo®, a leading global provider of connectivity and power solutions, recently announced the launch of the industry’s best high-gain 5G pre-driver, the QPA9822. The product can achieve a high gain of 39dB at 3.5GHz and a peak power of +29dBm. This new pre-driver for mMIMO base stations demonstrates Qorvo’s firm commitment to promoting the development of 5G technology and further consolidates its leadership in cellular infrastructure.

As a wideband, high-gain, high-linearity driver amplifier, the QPA9822 is designed for 32-node mMIMO systems. It can achieve up to 530MHz of 5G New Radio (NR) instantaneous signal bandwidth, which is very suitable for the N77 band that is critical to 5G deployment and other mMIMO applications.

“Qorvo’s QPA9822 not only provides the best high gain that can be achieved by 5G pre-drivers on the market today, but also creates a scalable solution for 32T and 64T wireless base stations. This helps ensure that 5G mMIMO systems are easily deployed in popular bands around the world.” said Debbie Gibson, product line director of Qorvo’s Wireless Infrastructure Business Unit.

The QPA9822 is internally matched to 50Ω impedance across the entire operating band of 3.3-4.2GHz and integrates a fast enable/disable function through the VEN pin. In addition, it also has external bias control capabilities to optimize linearity and support up to 530MHz of instantaneous bandwidth.

The QPA9822 uses a compact 16-pin, 3mm×3mm SMT package, which is size and pin compatible with the QPA9122M high-gain, high-linearity driver amplifier, and can be easily integrated into existing and new designs, thereby shortening the time to market for customers.

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Arteris, Inc. is a leading system IP provider dedicated to accelerating the creation of systems on chips (SoCs), and Andes Technology (Taiwan Stock Exchange: 6533) is a founding and principal member of the RISC-V International organization. Also a leading provider of high-performance/low-power RISC-V processor IP, today announced a partnership to advance RISC-V-based processors for artificial intelligence, 5G, networking, mobile, storage, AIoT and space applications. Innovation in SoC design.

The Andes QiLai RISC-V platform is a development board powered by the QiLai SoC, which is based on Andes’ RISC-V processor IP and Arteris FlexNoC interconnect IP for on-chip connectivity. The QiLai SoC integrates Andes 64-bit AX45MP multi-core processor (quad-core cluster) running at 2.2 GHz and NX27V vector processor running at 1.5 GHz, and uses Arteris Network-on-Chip (NoC) interconnect IP, which The IP features PCIe, DDR, SRAM and general IO subsystems using the AMBA AXI protocol. Supported software includes the OpenSUSE Linux distribution, AndeSight™ toolchain, AndeSoft™ software stack, and AndesAIRE™ NN SDK for converting AI/ML models into executable files.

Dr. Charlie Su, President and Chief Technology Officer of Andes Technology, said: “Despite the widespread use of AndesCore™ AX45MP and NX27V processors, we are pleased to see QiLai SoC’s first success on a new project. Arteris NoC IP is a flexible, The best choice for high-performance, top-level connectivity. The QiLai platform enhances rapid development and evaluation of RISC-V software and accelerates the expansion of the RISC-V ecosystem.”

Michal Siwinski, Chief Marketing Officer of Arteris, said: “We are excited to partner with Andes and support the interoperability of the QiLai platform to further accelerate the mainstream adoption of RISC-V technology. Our collaboration supports our goal to be a catalyst for SoC innovation. mission so that our mutual customers can focus on effectively creating the breakthroughs of the future.”

Arteris’ FlexNoC non-coherent NoC IP and Ncore cache-coherent NoC IP enable scalable, low-latency and energy-efficient on-chip communications to achieve superior performance in complex SoC designs. The technology facilitates the integration of high-performance, low-power CPU IP, enhancing system functionality and interoperability, especially within the growing RISC-V ecosystem. This configurable and adaptable interconnect solution connects seamlessly with a variety of components to reduce risk and accelerate time to market. System designers can leverage Arteris NoC IP to enhance the reliability and quality of next-generation SoCs by connecting well-tested CPU IP blocks.

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The semiconductor industry is characterized by relentless innovation, stringent quality standards, cost efficiency, and rapid market delivery. However, it also faces numerous challenges, including increasing design complexity, shrinking feature sizes, rising defect rates, and a growing demand for new materials and products. Now, artificial intelligence (AI) plays a crucial role in overcoming these obstacles and enhancing engineers’ productivity in chip manufacturing.

AI significantly reduces chip manufacturing costs by optimizing various aspects of the production process. Generative AI employs advanced reinforcement learning techniques, such as Deep Q Networks (DQN) and Monte Carlo Tree Search (MCTS), to optimize costs. These technologies predict the most promising outcomes by improving decision-making processes and evaluating placement options. This fine-tuning greatly reduces the time and resources engineers need for each chip design and manufacturing process, significantly lowering production costs while ensuring adherence to strict quality standards.

Streamlined Manufacturing Processes
Generative AI simplifies semiconductor manufacturing processes, particularly in supplier network optimization. It formulates multi-source strategies by sifting through extensive documentation and facilitates procurement from diverse suppliers based on criteria such as demand, availability, and proximity. AI-driven robots excel in negotiating costs, distilling vast amounts of data into coherent insights, and navigating complex performance metrics and supplier communications. This optimization ensures smooth supply chain operations, enhancing overall manufacturing efficiency.

Improved Wafer Fabrication
Wafer fabrication is a crucial step in semiconductor manufacturing, transforming non-conductive silicon wafers into substrates filled with integrated circuits. This process involves stages such as oxidation, photolithography, etching, and doping, each potentially impacting chip integrity. Generative AI, combined with advanced imaging technologies, significantly enhances defect detection rates by identifying anomalies that traditional methods might miss. This improvement mirrors the transformative impact of AI in other industries, such as logistics, where AI optimizes picking routes, delivery frameworks, and cost structures.

Achieving Sustainability with AI
Reducing Carbon Emissions
Generative AI plays a vital role in reducing CO2 emissions in the semiconductor industry. It optimizes energy usage and predicts demand to prevent overconsumption. AI-driven energy-efficient chip designs and streamlined supply chains further reduce environmental impact. Additionally, generative AI advances carbon capture technologies, decreasing atmospheric CO2 levels and promoting a green and sustainable future for semiconductor manufacturing.

The Present and Future of Chip Manufacturing
Many countries are heavily investing in new semiconductor manufacturing units to meet high chip demand. For instance, the US government proposed the CHIPS and Science Act of 2022, investing $52.7 billion in semiconductor manufacturing and research as part of a broader infrastructure plan. Over the next five years, approximately $1 trillion will be invested globally in expanding the industry, underscoring the urgency of the situation.

Traditional approaches to supply chain resilience are increasingly inadequate. AI-driven tools are set to become indispensable in chip design, potentially boosting engineer productivity, addressing the rising costs of designing complex chips at cutting-edge nodes, and bridging the engineering talent gap.

Conclusion
Integrating generative AI into the semiconductor industry promises unprecedented efficiency, innovation, and sustainability. As we tackle challenges and harness AI’s potential, we stand at a pivotal moment in redefining the semiconductor landscape, setting new benchmarks for quality, speed, and environmental responsibility.

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Vishay Intertechnology, Inc. (NYSE: VSH), based in Malvern, Pennsylvania, USA, and Shanghai, China, announced the launch of a new series of low-profile, aerospace-grade planar transformers for power conversion – the SGTPL-2516 series. Compared to traditional planar transformers, the customizable Vishay Custom Magnetics SGTPL-2516 series transformers offer lower cost, smaller size, and higher power density, providing significant advantages and meeting MIL-STD-981 Class S requirements.

Featuring through-hole terminals and various package sizes, these transformers find wide applications in switch-mode power supplies as well as DC/DC and AC/DC converters. Designed for harsh environments, they feature robust encapsulation with molded windings, operate at temperatures up to 130°C, and are certified according to MIL-STD-981. The SGTPL-2516 series transformers operate at frequencies ranging from 80 kHz to 300 kHz, with a high dielectric withstand voltage of 1500 VAC, power rating of 150 W, and leakage inductance of 0.5 H.

With a unique winding structure and manufacturing process, these transformers achieve a higher copper fill factor than traditional planar transformers, resulting in improvements in package size, efficiency, and power density. The winding technology of the SGTPL-2516 series enables adjustment of operating voltage, inductance, power, package size, and height according to specific design requirements, without incurring upfront tooling costs. In addition to MIL-STD-981 Class S Group A and B screening, these devices also offer Class P screening for design verification testing and other customized screening options.

Samples of these new transformers are now available, and they are in full production. The lead time for Class P screening devices is 8 weeks, while for Class S screening devices, it is 21 weeks.

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According to reports, in order to maintain America’s leading position in semiconductors, the United States needs robust trade policies to complement domestic efforts to accelerate development. This was the main message of public comments submitted by the SIA on April 22 in response to the U.S. Trade Representative’s request for information on how trade policies can enhance U.S. supply chain resilience.

President Biden signed into law the bipartisan Chips and Science Act in 2022 to incentivize the growth of the U.S. semiconductor ecosystem, strengthen its supply chain, and ensure the U.S. semiconductor industry remains globally competitive. Ultimately, this is a bold plan aimed at bringing more chip manufacturing back to the United States.

This historic move has already yielded significant results. Since the passage of the CHIPS Act, companies across the semiconductor ecosystem have announced over 80 new projects in the United States, with private investment now approaching $5 trillion. However, to ensure the long-term competitiveness of U.S. semiconductor companies and make the Chips Act more effective, a larger global market is needed to allow SIA members to sell chips domestically that they manufacture domestically.

In fact, 75% of the revenue for U.S.-headquartered semiconductor companies comes from sales to foreign markets. Unfortunately, despite U.S. government efforts to foster greater economic supply chain integration and resilience through the Indo-Pacific Economic Framework (IPEF) and the Americas Prosperity Partnership (APEP), U.S. chip exports declined by 14% last year.

SIA strongly recommends that the Office of the U.S. Trade Representative effectively utilize trade policies and pursue market-opening initiatives to stimulate global demand for U.S. semiconductors (as well as other goods manufactured domestically). Similarly, SIA encourages the U.S. Trade Representative to advocate for U.S. companies to re-engage in countering market access barriers and regulations imposed by other governments, which unfairly skew the competitive environment and disadvantage the U.S. semiconductor industry.

When navigating the twists and turns of global trade and technology, it’s evident that the future of the U.S. semiconductor industry depends not only on domestic investment but also on prudent strategic international partnerships and wise trade policies aimed at opening new markets for American chips.

SIA expresses its anticipation to continue collaborating with the U.S. government and other stakeholders, advocating for new ideas to pave the way for a more resilient, competitive, and sustainable U.S. semiconductor industry, driving future astonishing innovations.

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