The semiconductor industry is about to reach the wafer process bottlenecks, also on behalf of Moore’s Law will likely fail, the future is bound to integrate fab down to the packaging and testing plant in miniature wafer process can not continue, the packaging and testing industry will be temporarily to system-level packaging, etc. effective integration of chip technology will do to improve the chip manufacturing profits, provoked beyond the role of Moore’s Law, ASE, SPIL and force a positive layout.

Semiconductor Association Lu superior that the next vertically stacked semiconductor going to do 3D, the future of the global semiconductor industry will grow towards the kind of Moore’s Law.

Wafer miniature reach bottleneck

Ma Guanghua, deputy general manager SPIL R & D Center, said the future single chip has been unable to continue to narrow the case, say, or a reduced cost price has gone beyond economic benefits, it is necessary at this time through the packaging technology to enhance the performance benefits of the chip, like ASE system-in-package (SiP) technology or wafer level packaging.

Ma Guanghua pointed out that the so-called wafer level package is to direct the entire wafer packaging and testing process have lost part of the packaging materials, make up an IC (integrated circuit) will be relatively thin, so-called fan-out wafer level package that is directly on the fan-out wafer packaging materials can save another 30%, while the chip can be thinner.

There panel next level package, Ma Guanghua interpretation, the panel level package is the direct use of the panel encapsulation, compared to the 12-inch wafer cutting IC, can be more efficient and cost-effective, until the fan-out type package maturity on the panel after, there will be panel-level system-level package.

Panel level package cost savings

Now all major plant aimed at advanced packaging process to improve the quality of packaging and testing, but also to throw off opponents, which is actively layout ASE fan-out type package and system-in-package, the previous ASE also made DECA TECHNOLOGIES type of fan-out wafer level packaging process technology and patents.

Powertech chairman DK Tsai said that after due future product development will move towards compact size, but faced with the limits of Moore’s Law, it is necessary to take the advanced packaging technology to make up for this deficiency, whether 2.5D, 3D or fan-out (Fan out) packaging, etc., to force all devices are ready.

IC packaging and testing industry pointed out that at present, neither on logic IC or is NAND Flash, the 3D stacking technology is required in order to allow the chip to maximize the benefits of play, but also to achieve the slim and light level.

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